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acpl-071l and acpl-074l single-channel and dual-channel high speed 15 mbd cmos optocoupler with glitch-free power-up feature data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product features ? +3.3v and +5 v cmos compatibility ? 30 ns max. pulse width distortion ? 40ns max. propagation delay (for 3.3v supply voltage) ? 30 ns max. propagation delay skew ? high speed: 15 mbd min ? 10 kv/s minimum common mode rejection ? C40 to 105c temperature range ? glitch-free power-up feature ? safety and regulatory approvals: - ul recognized: 3750 v rms for 1 min. per ul 1577 - csa component acceptance notice #5 - iec/en/din en 60747-5-5 truth table led v o , output off h on l a 0.1uf bypass capacitor must be connected between pins 5 and 8. nc anode cathode nc 4 3 2 1 v dd v o1 anode1 cathode1 v o2 gnd cathode2 anode2 acpl-071l acpl-074l shield 5 6 7 8 4 3 2 1 shield v dd nc v o gnd 5 6 7 8 description the acpl-071l (single-channel) and acpl-074l (dual- channel) are 15 mbd cmos optocouplers in soic-8 pack - age. the optocouplers utilize the latest cmos ic technol - ogy to achieve outstanding performance with very low power consumption. basic building blocks of acpl-071l and acpl-074l are high speed leds and cmos detector ics. each detector incorporates an integrated photodiode, a high speed transimpedance amplifer, and a voltage comparator with an output driver. applications ? digital feld bus isolation: ? canbus, rs485, usb ? multiplexed data transmission ? computer peripheral interface ? microprocessor system interface ? dc/dc converter functional diagram
2 ordering information acpl-071l/074l are ul recognized with 3750 vrms for 1 minute per ul1577. part number option package surface mount tape & reel iec/en/din en 60747-5-5 quantity rohs compliant acpl-071l -000e so-8 x 100 per tube -500e x x 1500 per reel -060e x x 100 per tube -560e x x x 1500 per reel acpl-074l -000e so-8 x 100 per tube -500e x x 1500 per reel -060e x x 100 per tube -560e x x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: acpl-071l-500e to order product of small outline so-8 package in tape and reel packaging in rohs compliant. example 2: ACPL-074L-000E to order product of small outline so-8 package in tube packaging and rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. refow soldering profle recommended refow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used. regulatory information the acpl-071l and acpl-074l have been approved by the following organizations: ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca88324. iec/en/din en 60747-5-5
3 package dimensions acpl-071l and acpl-074l (small outline s0-8 package) xxxv yww 8 7 6 5 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. option number 500 not marked. note: floating lead protrusion is 0.15 mm (6 mils) max. 0.203 0.102 (0.008 0.004) 7 pin one 0 ~ 7 * * 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation
4 insulation and safety related specifcations parameter symbol value units conditions minimum external air gap (clearance) l(i01) 4.9 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(i02) 4.8 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 mm insulation thickness between emitter and detector; also known as distance through insulation. tracking resistance (comparative tracking index) cti 175 volts din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) all avago technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specifed for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fllets of the input and output leads must be considered. there are recom - mended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
5 iec/en/din en 60747-5-5 insulation characteristics* description symbol option 060 unit installation classifcation per din vde 0110, table 1 for rated mains voltage 150 vrms for rated mains voltage 300 vrms for rated mains voltage 600 vrms i C iv i C iv i C iii climatic classifcation 40/85/21 pollution degree (din vde 0110/39) 2 maximum working insulation voltage v iorm 567 vpeak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with tm=1 sec, partial discharge < 5 pc v pr 1063 vpeak input to output test voltage, method a* v iorm x 1.6 = v pr , type and sample test, tm=10 sec, partial discharge < 5 pc v pr 907 vpeak highest allowable overvoltage (transient overvoltage tini = 60 sec) v iotm 6000 vpeak safety-limiting values C maximum values allowed in the event of a failure. case temperature input current output power t s i s, input p s, output 150 150 600 c ma mw insulation resistance at t s , v io = 500 v r s 10 9 ? absolute maximum ratings parameter symbol min. max. units storage temperature t s C55 +125 c ambient operating temperature t a C40 +105 c supply voltages v dd 0 6.0 volts output voltage v o C0.5 v dd +0.5 volts average forward input current i f - 20.0 ma average output current i o - 10.0 ma input power dissipation p i 35 mw output power dissipation p o 100 mw lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder refow temperature profle see refow soldering profle recommended operating conditions parameter symbol min. max. units ambient operating temperature t a C40 +105 c supply voltages v dd 4.5 5.5 v 3.0 3.6 v input current (on) i f 9 18 ma supply voltage slew rate [1] s r 0.5 500 v/ms
6 electrical specifcations over recommended temperature (t a = C40c to +105c), 3.0v v dd 3.6v and 4.5 v v dd 5.5 v. all typical specifcations are at t a =+25c, v dd = +3.3v. parameter symbol part number min. typ. max. units test conditions input forward voltage v f 1.3 1.5 1.8 v i f = 14ma input reverse breakdown voltage bv r 5.0 v i r = 10 a logic high output voltage v oh v dd -1 v dd -0.3 v i f = 0, i o = -4 ma, v dd =3.3v v dd -1 v dd -0.2 v i f = 0, i o = -4 ma, v dd =5v logic low output voltage v ol 0.35 0.8 v i f = 14ma, i o =4ma, v dd =3.3v 0.2 0.8 v i f = 14ma, i o = 4ma, v dd =5v input threshold current i th 4.5 8.8 ma i ol = 20 a logic low output supply current i ddl acpl-071l 4.1 6.0 ma i f = 14 ma acpl-074l 8.3 12.0 ma i f = 14 ma logic low output supply current i ddh acpl-071l 3.8 6.0 ma i f = 0 acpl-074l 7.6 12.0 ma i f = 0 switching specifcations over recommended temperature (t a = C40c to +105c), 3.0v v dd 3.6v and 4.5 v v dd 5.5 v. all typical specifcations are at t a =+25c, v dd = +3.3v. parameter symbol min. typ. max. units test conditions propagation delay time to logic low output [2] t phl 29 40 ns i f = 14ma, c l = 15pf, v dd =3.3v cmos signal levels 50 ns i f = 14ma, c l = 15pf, v dd =5v cmos signal levels propagation delay time to logic high output [2] t plh 22 40 ns i f = 14ma, c l = 15pf, v dd =3.3v, cmos signal levels 50 ns i f = 14ma, c l = 15pf, v dd =5v, cmos signal levels pulse width t pw 66.7 ns pulse width distortion [3] |pwd | 0 7 25 ns i f = 14ma, c l = 15pf, v dd =3.3v, cmos signal levels 30 ns i f = 14ma, c l = 15pf, v dd =5v, cmos signal levels propagation delay skew [4] t psk 30 ns i f = 14ma, c l = 15pf cmos signal levels output rise time (10% C 90%) t r 20 ns i f = 14ma, c l = 15pf cmos signal levels output fall time (90% - 10%) t f 25 ns i f = 14ma, c l = 15pf cmos signal levels common mode transient immunity at logic high output [5] | cm h | 10 15 kv/s v cm = 1000 v, t a = 25c, i f = 0 ma common mode transient immunity at logic low output [6] | cm l | 10 15 kv/s v cm = 1000 v, t a = 25c, i f = 14 ma
7 0.001 0.01 0.1 1 10 100 1000 1.1 1.2 1.3 1.4 1.5 1.6 v f -forward voltage-v i f -forward current-ma i f v f t a =25 c 0 2 4 6 8 10 12 -40 -20 0 20 40 60 80 100 t a -temperature- o c i ddh -logic high output supply current -ma v dd =5.0v v dd =3.3v 0 1 2 3 4 5 6 -40 -20 0 20 40 60 80 100 120 t a -temperature- o c i th -input threshold current-ma 5v 3.3v i ol =20ua 0 2 4 6 8 10 12 -40 -20 0 20 40 60 80 100 t a -temperature- o c i ddl -logic low output supply current-ma v dd =5.0v v dd =3.3v figure 1. typical input diode forward characteristic. figure 2. typical input threshold current vs. temperature. figure 3. typical logic high o/p supply current vs. temperature for acpl-074l. figure 4. typical logic low o/p supply current vs. temperature for acpl-074l. package characteristics all typical at t a = 25 c. parameter symbol min. typ. max. units test conditions input-output insulation i i-o 1.0 a 45% rh, t = 5 s v i-o = 3 kv dc, t a = 25c input-output momentary withstand voltage v iso 3750 vrms rh 50%, t = 1 min., t a = 25c input-output resistance r i-o 10 12 w v i-o = 500 v dc input-output capacitance c i-o 0.6 pf f = 1 mhz, t a = 25c notes: 1. slew rate of supply voltage ramping is recommended to ensure no glitch more than 1v to appear at the output pin. 2. t phl propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the falling edge of the v o signal. t plh propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the rising edge of the v o signal. 3. pwd is defned as |t phl - t plh |. 4. t psk is equal to the magnitude of the worst case diference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 5. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 6. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
8 0 5 10 15 20 25 30 35 40 45 50 6 7 8 9 10 11 12 13 14 15 16 i f ? pulse input current ? ma t p ? propagation delay; pwd-pulse width distortion ? ns t phl ch1 t phl ch2 t plh ch1 t plh ch2 pwd ch1 pwd ch2 v dd =5v t a =25 c 0 5 10 15 20 25 30 35 40 45 50 6 7 8 9 10 11 12 13 14 15 16 i f ? pulse input current ? ma t p ? propagation delay; pwd-pulse width distortion ? ns t phl ch1 t phl ch2 t plh ch1 t plh ch2 pwd ch1 pwd ch2 v dd =3.3v t a =25 c 1 . 3 5 1 . 4 1 . 4 5 1 . 5 1 . 5 5 1 . 6 1 . 6 5 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 t a -temperature- o c v f -forward voltage-v figure 5. typical switching speed vs. pulse input current at 5v supply voltage. figure 6. typical switching speed vs. pulse input current at 3.3v supply voltage. application information bypassing and pc board layout the acpl-071l and acpl-074l optocouplers are extreme - ly easy to use. acpl-071l and acpl-074l provide cmos logic output due to the high-speed cmos ic technology used. the external components required for proper operation are the input limiting resistor and the output bypass ca - pacitor. capacitor values should be between 0.01 f and 0.1 f. for each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. figure 8. recommended printed circuit board layout gnd1 7 5 6 8 2 3 4 1 gnd2 c nc v dd v o i f xxx yww 7 5 6 8 2 3 4 1 gnd 2 c v dd gnd 1 xxx yww v o2 v o1 i f1 gnd 1 i f2 acpl-071l acpl-074l figure 7 typical v f vs. temperature. c = 0.01 m f to 0.1 m f
9 propagation delay, pulse-width distortion and propa - gation delay skew propagation delay is a fgure of merit which describes how quickly a logic signal propagates through a system. the propagation delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propa - gate to the output, causing the output to change from high to low (see figure 9). pulse-width distortion (pwd) results when t plh and t phl difer in value. pwd is defned as the diference between t plh and t phl and often pwd is defned as the diference between t plh and t phl and often determines the maxi - mum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20-30% of the minimum pulse width is tolerable; the exact fgure depends on the particular application (rs232, rs422, t-1, etc.). propagation delay skew, t psk , is an important parameter to consider in parallel data applications where synchroni - zation of signals on parallel data lines is a concern. if the parallel data is being sent through a group of opto - couplers, diferences in propagation delays will cause the data to arrive at the outputs of the optocouplers at difer - ent times. if this diference in propagation delays is large enough, it will determine the maximum rate at which par - allel data can be sent through the optocouplers. propagation delay skew is defned as the diference be - tween the minimum and maximum propagation delays, either t plh or t phl , for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temper - ature). as illustrated in figure 10, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the diference between the shortest propaga - tion delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can de - termine the maximum parallel data transmission rate. figure 10 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. the fgure shows data and clock signals at the inputs and outputs of the optocou - plers. to obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. propagation delay skew represents the uncertainty of where an edge might be after being sent through an opt - ocoupler. figure 10 shows that there will be uncertainty in both the data and the clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. data inputs clock data outputs clock t psk t psk 50% 50% t psk i f v o i f v o 50%, cmos 50%, cmos figure 9. propagation delay and skew waveform figure 10. parallel data transmission example
10 the t psk specifed optocouplers ofer the advantages of guaranteed specifcations for propagation delays, pulse- width distortion and propagation delay skew over the rec - ommended temperature, and power supply ranges. powering sequence v dd needs to achieve a minimum level of 3.0v before powering up the output connecting component. input limiting resistors acpl-071l and acpl-074l are direct current driven (fig - ure 8), and thus eliminate the need for input power sup - ply. to limit the amount of current fowing through the led, it is recommended that a 210ohm resistor is connect - ed in series with anode of led (i.e. pin 2 for acpl-071l and pin 1 and 4 for acpl-074l) at 5v input signal. at 3.3v input signal, it is recommended to connect 80ohm resistor in se - ries with anode of led. the recommended limiting resistors are based on the assumption that the driver output impedence is 50? (as shown in figure 11). speed improvement a peaking capacitor can be placed across the input cur - rent limit resistor (figure 11) to achieve enhanced speed performance. the value of the peaking cap is dependent to the rise and fall time of the input signal and supply volt - ages and led input driving current (i f ). figure 12 shows signifcant improvement of propagation delay and pulse with distortion with added peak capacitor at driving cur - rent of 14ma and 3.3v or 5v power supply. figure 11 connection of peaking capacitor (cpeak) in parallel of the input limiting resistor (rllimit) to improve speed performance figure 12. improvement of t p and pwd with added 100pf peaking capacitor in parallel of input limiting resistor. t a - temperature - o c t p - propagation delay; pwd-pulse width distortion -ns t a - temperature - o c t p - propagation delay; pwd-pulse width distortion -ns 0 . 0 0 5 . 0 0 1 0 . 0 0 1 5 . 0 0 2 0 . 0 0 2 5 . 0 0 3 0 . 0 0 3 5 . 0 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 t phl t plh t plh t phl |pwd| with peaking cap without peaking cap 0.00 5.00 10.00 15.00 20.00 25.00 30.00 -40 -20 0 20 40 60 80 100 t phl t plh t plh t phl |pwd| with peaking cap without peaking cap (i) v dd =3.3v, c peak =100pf, r limit =80 (ii) v dd =5v, c peak =100pf, r limit =210 g n d 2 v d d 2 0 . 1 f g n d 1 r l i m i t s h i e ld v in + - c pe a k v o r d r v =5 0
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. av02-0963en - september 19, 2013 gnd 2 v dd2 v o monitoring note v cm 0.1f r limit shield i f a b + - pulse gen. zo=50 v o gnd2 o v (min.) v dd 0 v switch at a: i = 0 ma f switch at b: i = 14 ma f cm v h cm cm l o v (max.) cm v (peak) v o figure 13. test circuit for common mode transient immunity and typical waveforms. r total is the total resistance of the driver output impedence (which is assumed to be 50 ?) and the limiting resistor (r total =r drv +r limit ) .

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